Job Description

MS or PhD in EECS, ECE, or related computing discipline
7-10 years of experience in development memory sub-systems or high performance CPUs
5+ years of experience in Interconnect, Coherency controller or CPU core RTL design
Experience with Physical design flow from high level design to synthesis, place and route, timing and power optimization
knowledge of Verilog/SystemVerilog, DC, ICC, and Primetime
Understanding of trade off and optimization technique between Performance, Power and Area
General scripting and programming skills (Python, Perl, C/C++, etc.)
Formal Verification experience would be a plus


  • Training Engineer