Hands on experience with the implementation (PnR Signoff) of complex high speed SoC designs in cutting edge process technologies ( 22nm,16, 7nm etc).
Hands on experience in handling the tapeout of complex high speed SoC designs in cutting edge process technologies
Floor Planning, Power Plan, Place and Route, Clock Planning and Clock Tree Synthesis, Parasitic Extraction
Strong expertise in Static Timing analysis , constraint development and sign off.
Innovate on the flows to meet the QoR targets and ensure predictability
Good understanding on device/interconnect and circuit aspect of the complex UDSM technologies is an added advantage.
Being proficient in TCL, Perl etc.
Have lead Physical Design engineers in the past will be a plus
- Project manager