Bachelor's degree in Electrical Engineering or Computer Science or equivalent practical experience.
Experience verifying digital logic at RTL using SystemVerilog for FPGAs and ASICs.
Experience verifying digital systems with standard IP components/interconnects, including microprocessor cores and hierarchical memory subsystems.
Experience creating/using verification components and environments in methodology (VMM, OVM, UVM).
Master's degree in Electrical Engineering or Computer Science with 3 years of relevant experience, or PhD in Electrical Engineering or Computer Science.
Experience with image processing, computer vision, and/or machine learning applications.
Experience prototyping and debugging systems on Field Programmable Gate Array (FPGA) platforms.
Experience with performance verification of ASIC components.
Experience with verification techniques.
Familiarity with ASIC standard interfaces and memory system architecture.
- Design Engineer