Own ASIC verification of IP/Cluster for complicated designs in RTL.
Work with HW architects and designers to make the right implementation choices.
Interact with the Performance verification teams to augment verification through dynamic simulations and/or Formal verification techniques.
You will work with the specifications and ensure functional and code coverage of all the RTL which you will verify.
Work with and enable FPGA and S/W teams to ensure that S/W is tested.
You will be involved with post-silicon verification and debug
What we need to see:
BS / MS with 2+ years of design experience
Experience in ASIC verification of complex design units for at least one or two projects
Exposure to design and verification tools (VCS or equivalent simulation tools, debug tools like Debussy, GDB)
Exposure to System Verilog and UVM based methodology for ASIC verification is highly desired.
Ways to stand out from the crowd:
Knowledge of Memory controllers or prior experience with verification of IP/clusters involving access to Memory.
Working knowledge of DRAM specifications like HBM and LPDDRx memory standards.
Good debugging and problem solving skills
Scripting knowledge (Python/Perl/shell)
Good interpersonal skills and ability & desire to work as a part of a team
- Design Engineer