Job Description

BE with 5+ years of relevant experience / MTech with 3+ years of relevant experience in Electrical Engineering or Computer Engineering or other relevant field of study
Hands on experience with creating micro-architecture and RTL design from Functional Specifications for medium design complexity
Knowledge of one or more of standard protocols: Ethernet/USB/SD-MMC/AMBA (AMBA2, AXI)/ MIPI.
Knowledge of Ethernet domain is preferred
Worked on control path oriented designs like asynchronous FIFO, DMA architectures, SPRAM/ DPRAM interface design
Hands on experience with Verilog/ System Verilog coding and Simulation tools
Hand-on experience and good conceptual knowledge of lint, CDC, RDC, synthesis, constraints, timing analysis, power analysis, formal checking
Knowledge of Low Power Design Methodology is desired
Good communication and problem solving skills

Preferred Experience
Understands Specifications/Protocol, functional specifications, feature for the IP core and create micro-architecture and detailed design documents for its components
Works on various aspects of the digital design development flow which includes RTL development, lint, CDC, RDC, synthesis, timing analysis, power analysis, formal checking
Performs unit level testing in Verilog test bench environment and identify test plan
Analyses the coverage metrics and improve them with identification of additional test cases
Understands and follows IP development specific processes


  • Senior Design Engineer